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february 2004 ordering numbers: STA013$ (so28) STA013t$ (tqfp44) STA013b$ (lfbga 8x8) single chip mpeg2 layer 3 decoder supporting: - all features specified for layer iii in iso/iec 11172-3 (mpeg 1 audio) - all features specified for layer iii in iso/iec 13818-3.2 (mpeg 2 audio) - lower sampling frequencies syntax extension, (not specified by iso) called mpeg 2.5 decodes layer iii stereo channels, dual channel, single channel (mono) supporting all the mpeg 1 & 2 sam- pling frequencies and the exten- sion to mpeg 2.5: 48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 khz accepts mpeg 2.5 layer iii elemen- tary compressed bitstream with data rate from 8 kbit/s up to 320 kbit/s digital volume control digital bass & treble control serial bitstream input interface ancillary data extraction via i2c in- terface. serial pcm output interface (i 2 s and other formats) pll for internal clock and for out- put pcm clock generation low power consumption: 85mw at 2.4v crc check and synchronisation er- ror detection with software indi- cators i 2 c control bus low power 3.3v cmos technology 10 mhz, 14.31818 mhz, or 14.7456 mhz external input clock or built-in in- dustry standard xtal oscillator different frequencies may be sup- ported upon request to stm applications pc sound cards multimedia players description the STA013 is a fully integrated high flexibility mpeg layer iii audio decoder, capable of de- coding layer iii compressed elementary streams, as specified in mpeg 1 and mpeg 2 iso stand- ards. the device decodes also elementary streams compressed by using low sampling rates, as speci- fied by mpeg 2.5. STA013 receives the input data through a serial input interface. the decoded signal is a stereo, mono, or dual channel digital output that can be sent directly to a d/a converter, by the pcm out- put interface. this interface is software program- mable to adapt the STA013 digital output to the most common dacs architectures used on the market. the functional STA013 chip partitioning is de- scribed in fig.1. STA013 STA013b STA013t mpeg 2.5 layer iii audio decoder ? so28 tqfp44 lfbga64 1/38
i 2 c control serial input interface buffer mpeg 2.5 layer iii decoder core channel config. & volume control output buffer pcm output interface parser 26 3 4 reset sda scl 5 6 7 bit_en sckr sdi sdo 9 10 11 sckt lrckt system & audio clocks test interface src_int out_clk/data_req xti xto oclk testen scanen d98au965 8 28 2120122425 figure 1. block diagram: mpeg 2.5 layer iii decoder hardware partitioning. thermal data symbol parameter value unit r th j-amb thermal resistance junction to ambient 85 c/w absolute maximum ratings symbol parameter value unit v dd power supply -0.3 to 4 v v i voltage on input pins -0.3 to v dd +0.3 v v o voltage on output pins -0.3 to v dd +0.3 v t stg storage temperature -40 to +150 c t oper operative ambient temp -40 to +85 (*) c t j operating junction temperature -40 to 125 c (*) guaranteed by design. STA013 - STA013b - STA013t 2/38
figure 2. pin connection vdd_1 vss_1 reset sda scl sckr sdi bit_en sdo vdd_4 vss_4 xti filt xto pvss pvdd vdd_3 vss_3 1 3 2 4 5 6 7 8 9 26 25 24 23 22 20 21 19 27 10 28 vdd_2 testen d98au911a vss_2 sckt lrckt vss_5 src_int scanen 11 12 13 18 16 17 15 14 oclk out_clk/data_req 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 n.c. lrckt oclk n.c. vss_2 vdd_2 vss_3 vdd_3 n.c. pvdd pvss filt xto n.c. xti n.c. n.c. n.c. vss_4 n.c. vdd_4 testen sdi n.c. sckr n.c. bit_en n.c. src_int n.c. sdo n.c. sckt n.c. scanen reset vss_5 out_clk/data_rec n.c. vdd_1 vss_1 sda scl n.c. d99au1019 12 13 14 15 16 so28 tqfp44 a a1 = sdi b2 = sckr d4 = bit_en d1 = src_int e2 = sdo f2 = sckt h1 = lrckt h3 = oclk f3 = vss_2 e4 = vdd_2 g4 = vss_3 g5 = vdd_3 f5 = pvdd g6 = pvss 1 2 3 4 5 6 7 8 b c d e f g h d99au1085 g7 = filt g8 = xto f7 = xti e7 = vss4 c8 = vdd4 d7 = testen a7 = scanen b6 = reset a5 = vss5 c5 = out_clk/data_req b5 = vdd1 b4 = vss1 a4 = sda b3 = scl lfbga64 STA013 - STA013b - STA013t 3/38
pin description so28 tqfp44 lfbga64 pin name type function pad description 1 29 b5 vdd_1 supply voltage 2 30 b4 vss_1 ground 3 31 a4 sda i/o i 2 c serial data + acknowledge cmos input pad buffer cmos 4ma output drive 432 b3 scl ii 2 c serial clock cmos input pad buffer 5 34 a1 sdi i receiver serial data cmos input pad buffer 6 36 b2 sckr i receiver serial clock cmos input pad buffer 7 38 d4 bit_en i bit enable cmos input pad buffer with pull up 840 d1 src_int i interrupt line for s.r. control cmos input pad buffer 9 42 e2 sdo o transmitter serial data (pcm data) cmos 4ma output drive 10 44 f2 sckt o transmitter serial clock cmos 4ma output drive 11 2 h1 lrckt o transmitter left/right clock cmos 4ma output drive 12 3 h3 oclk i/o oversampling clock for dac cmos input pad buffer cmos 4ma output drive 13 5 f3 vss_2 ground 14 6 e4 vdd_2 supply voltage 15 7 g4 vss_3 ground 16 8 g5 vdd_3 supply voltage 17 10 f5 pvdd pll power 18 11 g6 pvss pll ground 19 12 g7 filt o pll filter ext. capacitor conn. 20 13 g8 xto o crystal output cmos 4ma output drive 21 15 f7 xti i crystal input (clock input) specific level input pad (see paragraph 2.1) 22 19 e7 vss_4 ground 23 21 c8 vdd_4 supply voltage 24 22 d7 testen i test enable cmos input pad buffer with pull up 25 24 a7 scanen i scan enable cmos input pad buffer 26 25 b6 reset i system reset cmos input pad buffer with pull up 27 26 a5 vss_5 ground 28 27 c5 out_clk/ data_req o buffered output clock/ data request signal cmos 4ma output drive note: src_int signal is used by STA013 internal software in broadcast mode only; in multimedia mode src_int must be connected to v dd in functional mode testen must be connected to vdd, scanen to ground. STA013 - STA013b - STA013t 4/38
1. electrical characteristics: v dd = 2.7v 0.3v; t amb = 0 to 70c; rg = 50 ? unless otherwise specified dc operating conditions symbol parameter value v dd power supply voltage 2.4 to 3.6v general interface electrical characteristics symbol parameter test condition min. typ. max. unit note i il low level input current without pull-up device v i = 0v -10 10 a1 i ih high level input current without pull-up device v i = v dd = 3.6v -10 10 a1 v esd electrostatic protection leakage < 1 a 2000 v 2 note 1: the leakage currents are generally very small, < 1na. the value given here is a maximum that can occur after an electrostatic stress on the pin. note 2: human body model. dc electrical characteristics symbol parameter test condition min. typ. max. unit note v il low level input voltage 0.2*v dd v v ih high level input voltage 0.8*v dd v v ol low level output voltage i ol = xma 0.4v v 1, 2 v oh high level output voltage 0.85*v dd v1, 2 note 1: takes into account 200mv voltage drop in both supply lines. note 2: x is the source/sink current under worst case conditions and is reflected in the name of the i/o cell according to the drive c apability. symbol parameter test condition min. typ. max. unit note i pu pull-up current v i = 0v; pin numbers 7, 24 and 26; v dd = 3v -25 -66 -125 a1 r pu equivalent pull-up resistance 50 k ? note 1: min. condition: v dd = 2.4v, 125c min process max. condition: v dd = 3.6v, -20c max. power dissipation symbol parameter test condition min. typ. max. unit note pd power dissipation @ v dd = 3v sampling_freq 24 khz 76 mw sampling_freq 32 khz 79 mw sampling_freq 48 khz 85 mw STA013 - STA013b - STA013t 5/38
v dd 100nf 1 2 v dd 100nf 14 13 v ss v dd 100nf 16 15 v dd 100nf 23 22 v ss v ss v ss 17 18 27 28 26 reset 24 testen 25 scanen out_clk/data_req v dd pv ss pv dd 100nf 4.7 f 4.7 f pv dd pv ss v ss 10k 1k 4.7nf pv ss 470pf 19 20 21 8 7 6 5 12 11 10 9 4 3 xto xti scr_int bit_en sckr sdi oclk lrckt sckt sdo scl sda d98au966 figure 3. test circuit i ol i oh c l v ref v dd output d98au967 figure 4. test load circuit output i ol i oh c l v ref sda 1ma 100pf 3.6v other outputs 100 a 100 a 100pf 1.5v test load 2. functional description 2.1 - clock signal the STA013 input clock is derivated from an ex- ternal source or from a industry standard crystal oscillator, generating input frequencies of 10, 14.31818 or 14.7456 mhz. other frequencies may be supported upon re- quest to stmicroelectronics. each frequency is supported by downloading a specific configura- tion file, provided by stm xti is an input pad with specific levels. symbol parameter test condition min. typ. max. unit v il low level input voltage v dd -1.8 v v ih high level input voltage v dd -0.8 v cmos compatibility the xti pad low and high levels are cmos compatible; xti pad noise margin is better than typical cmos pads. ttl compatibility the xti pad low level is compatible with ttl while the high level is not compatible (for example if v dd = 3v ttl min high level = 2.0v while xti min high level = 2.2v) STA013 - STA013b - STA013t 6/38
sclk_pol=0 sclk_pol=4 data ignored data valid sckr sckr sdi bit_en d98au968a data ignored figure 6. serial input interface clocks data source p mpeg decoder iic d98au912 iic sdo sckt lrckt serial audio interface sdi sckr bit_en xto dac rx tx xti filt pll oclk scl sda data_req figure 5. mpeg decoder interfaces. 2.2 - serial input interface STA013 receives the input data (msb first) thought the serial input interface (fig.5). it is a serial communication interface connected to the sdi (serial data input) and sckr (receiver se- rial clock). the interface can be configured to receive data sampled on both rising and falling edge of the sckr clock. the bit_en pin, when set to low, forces the bit- stream input interface to ignore the incoming data. for proper operation bit-e n line shold be toggled only when scr is stable low (for both sclk_pol configuration) the possible configu- rations are described in fig. 6. 2.3 - pll & clock generator system when STA013 receives the input clock, as de- scribed in section 2.1, and a valid layer iii input bit stream, the internal pll locks, providing to the dsp core the master clock (dclk), and to the audio output interface the nominal frequencies of the incoming compressed bit stream. the STA013 pll block diagram is described in figure 7. the audio sample rates are obtained dividing the oversampling clock (oclk) by software program- mable factors. the operation is done by STA013 embedded software and it is transparent to the user. the STA013 pll can drive directly most of the commercial dacs families, providing an over sampling clock, oclk, obtained dividing the vco frequency with a software programmable dividers. STA013 - STA013b - STA013t 7/38
r c c xti2dspclk xt i2oclk x s n m pfd cp vco switchin g circuit oclk dclk u p date frac frac xti disable pll figure 7. pll and clocks generation system 2.4 - pcm output interface the decoded audio data are output in serial pcm format. the interface consists of the following sig- nals: sdo pcm serial data output sckt pcm serial clock output lrclk left/right channel selection clock the output samples precision is selectable from 16 to 24 bits/word, by setting the output precision with pcmconf (16, 18, 20 and 24 bits mode) register. data can be output either with the most significant bit first (ms) or least significant bit first (ls), selected by writing into a flag of the pcmconf register. figure 8 gives a description of the several STA013 pcm output formats. the sample rates set decoded by STA013 is de- scribed in table 1. lrckt sdo sdo pcm_format = 0 pcm_diff = 0 pcm_format = 1 pcm_diff = 1 32 sclk c y cles 32 sclk c y cles 32 sclk c y cles 32 sclk c y cles 32 sclk c y cles m s m s l s l s l s l s m s m s m s l s m s l s l s l s m s m s lrckt sdo sdo pcm_ord = 1 pcm_prec is 16 bit mode pcm_ord = 0 pcm_prec is 16 bit mode 16 sclk c y cles 16 sclk c y cles 16 sclk c y cles 16 sclk c y cles 16 sclk c y cles m s m s l s l s l s l s m s m s m s l s m s l s l s l s m s m s sdo pcm_format = 0 pcm_diff = 1 l s l s m s m s m s l s l s m s sdo pcm_format = 1 pcm_diff = 1 l s l s m s m s m s l s l s m s 0 0 0 0 0 0 0 0 00 00 0 0 0 0 msb msb msb msb figure 8. pcm output formats table 1: mpeg sampling rates (khz) mpeg 1 mpeg 2 mpeg 2.5 48 24 12 44.1 22.05 11.025 32 16 8 STA013 - STA013b - STA013t 8/38
2.5 - STA013 operation mode the STA013 can work in two different modes, called multimedia mode and broadcast mode. in multimedia mode , STA013 decodes the in- coming bitstream, acting as a master of the data communication from the source to itself. this control is done by a specific buffer manage- ment, controlled by STA013 embedded software. the data source, by monitoring the data_req line, send to STA013 the input data, when the signal is high (default configuration). the communication is stopped when the data_req line is low. in this mode the fractional part of the pll is dis- abled and the audio clocks are generated at nominal rates. fig. 9 describes the default data_req signal behaviour. programming STA013 it is possible to invert the polarity of the data_req line (register req_pol). in broadcast mode , STA013 works receiving a bitstream with the input speed regulated by the source. in this configuration the source has to guarantee that the bitrate is equivalent to the nominal bitrate of the decoded stream. to compensate the difference between the nomi- nal and the real sampling rates, the STA013 em- bedded software controls the fractional pll op- eration. portable or mobile applications need normally to operate in broadcast mode. in both modes the mpeg synchronisation is automatic and transparent to the user. to operate in multi- media mode, the STA013, pin nr. 8, scr-int must be connected to vdd on the application board. 2.6 - STA013 decoding states there are three different decoder states: idle, init, and decode. commands to change the de- coding states are described in the STA013 i 2 c registers description. idle mode in this mode the decoder is waiting for the run command. this mode should be used to initialise the configuration register of the device. the dac connected to STA013 can be initialised during this mode (set mute to 1). play mute clock state pcm output x 0 not running 0 x 1 running 0 init mode "play" and "mute" changes are ignored in this mode. the internal state of the decoder will be updated only when the decoder changes from the state "init" to the state "decode". the "init" phase ends when the first decoded samples are at the output stage of the device. decode mode this mode is completely described by the follow- ing table: play mute clock state pcm output decoding 0 0 not running 0 no 0 1 running 0 no 1 0 running decoded samples yes 1 1 running 0 yes 3 - i 2 c bus specification the STA013 supports the i 2 c protocol. this pro- tocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the others as the slave. the master always starts the transfer and provides the serial clock for synchro- nisation. the STA013 is always a slave device in all its communications. 3. 1 - communication protocol 3.1.0 - data transition or change data changes on the sda line must only occur when the scl clock is low. sda transition while the clock is high are used to identify start or stop condition. 3.1.1 - start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is stable in the high state. a start condition must precede any command for data transfer. source send data to STA013 data_req source stops transmitting data source stops transmitting data d98au913 figure 9. STA013 - STA013b - STA013t 9/38
3.1.2 - stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition termi- nates communications between STA013 and the bus master. 3.1.3 - acknowledge bit an acknowledge bit is used to indicate a success- ful data transfer. the bus transmitter, either mas- ter or slave, releases the sda bus after sending 8 bit of data. during the 9th clock pulse the receiver pulls the sda bus low to acknowledge the receipt of 8 bits of data. 3.1.4 - data input during the data input the STA013 samples the sda signal on the rising edge of the clock scl. for correct device operation the sda signal has to be stable during the rising edge of the clock and the data can change only when the scl line is low. 3.2 - device addressing to start communication between the master and the STA013, the master must initiate with a start condition. following this, the master sends onto the sda line 8 bits (msb first) corresponding to the device select address and read or write mode. the 7 most significant bits are the device address identifier, corresponding to the i 2 c bus definition. for the STA013 these are fixed as 1000011. the 8th bit (lsb) is the read or write operation rw, this bit is set to 1 in read mode and 0 for write mode. after a start condition the STA013 identifies on the bus the device address and, if a match is found, it acknowledges the identification on sda bus during the 9th bit time. the following byte after the device identification byte is the in- ternal space address. 3.3 - write operation (see fig. 10) following a start condition the master sends a device select code with the rw bit set to 0. the STA013 acknowledges this and waits for the byte of internal address. after receiving the internal bytes address the STA013 again responds with an acknowledge. 3.3.1 - byte write in the byte write mode the master sends one data byte, this is acknowledged by STA013. the mas- ter then terminates the transfer by generating a stop condition. 3.3.2 - multibyte write the multibyte write mode can start from any inter- nal address. the transfer is terminated by the master generating a stop condition. dev-addr ack start d98au826a rw data no ack stop current address read dev-addr ack start rw sub-addr ack dev-addr ack stop random address read data no ack start rw dev-addr ack start data ack data ack stop sequential current read data no ack dev-addr ack start rw sub-addr ack dev-addr ack sequential random read data ack start rw data ack no ack stop data rw= high figure 11. read mode sequence dev-addr ack start d98au825b rw sub-addr ack data in ack stop byte write dev-addr ack start rw sub-addr ack data in ack stop multibyte write data in ack figure 10. write mode sequence STA013 - STA013b - STA013t 10/38
3.4 - read operation (see fig. 11) 3.4.1 - current byte address read the STA013 has an internal byte address counter. each time a byte is written or read, this counter is incremented. for the current byte address read mode, follow- ing a start condition the master sends the de- vice address with the rw bit set to 1. the STA013 acknowledges this and outputs the byte addressed by the internal byte address counter. the master does not acknowledge the received byte, but terminates the transfer with a stop condition. 3.4.2 - sequential address read this mode can be initiated with either a current address read or a random address read. how- ever in this case the master does acknowledge the data byte output and the STA013 continues to output the next byte in sequence. to terminate the streams of bytes the master does not acknowledge the last received byte, but terminates the transfer with a stop condition. the output data stream is from consecutive byte addresses, with the internal byte address counter automatically incremented after one byte output. 4 - i 2 c registers the following table gives a description of the mpeg source decoder (STA013) register list. the first column (hex_cod) is the hexadecimal code for the sub-address. the second column (dec_cod) is the decimal code. the third column (description) is the descrip- tion of the information contained in the register. the fourth column (reset) inidicate the reset value if any. when no reset value is specifyed, the default is "undefined". the fifth column (r/w) is the flag to distinguish register "read only" and "read and write", and the useful size of the register itself. each register is 8 bit wide. the master shall oper- ate reading or writing on 8 bits only. i 2 c registers hex_cod dec_cod description reset r/w $00 0 version r (8) $01 1 ident 0xac r (8) $05 5 pllctl [7:0] 0xa1 r/w (8) $06 6 pllctl [20:16] (mf[4:0]=m) 0x0c r/w (8) $07 7 pllctl [15:12] (idf[3:0]=n) 0x00 r/w (8) $0b 11 reserved $0c 12 req_pol 0x01 r/w (8) $0d 13 sclk_pol 0x04 r/w (8) $0f 15 error_code 0x00 r (8) $10 16 soft_reset 0x00 w (8) $13 19 play 0x01 r/w(8) $14 20 mute 0x00 r/w(8) $16 22 cmd_interrupt 0x00 r/w(8) $18 24 data_req_enable 0x00 r/w(8) $40 64 syncstatus 0x00 r (8) $41 65 anccount_l 0x00 r (8) $42 66 anccount_h 0x00 r (8) STA013 - STA013b - STA013t 11/38
i 2 c registers (continued) hex_cod dec_cod description reset r/w $43 67 head_h[23:16] 0x00 r(8) $44 68 head_m[15:8] 0x00 r(8) $45 69 head_l[7:0] 0x00 r(8) $46 70 dla 0x00 r/w (8) $47 71 dlb 0xff r/w (8) $48 72 dra 0x00 r/w (8) $49 73 drb 0xff r/w (8) $50 80 mfsdf_441 0x00 r/w (8) $51 81 pllfrac_441_l 0x00 r/w (8) $52 82 pllfrac_441_h 0x00 r/w (8) $54 84 pcm divider 0x03 r/w (8) $55 85 pcmconf 0x21 r/w (8) $56 86 pcmcross 0x00 r/w (8) $59 89 anc_data_1 [7:0] 0x00 r (8) $5a 90 anc_data_2 [15:8] 0x00 r (8) $5b 91 anc_data_3 [23:16] 0x00 r (8) $5c 92 anc_data_4 [31:24] 0x00 r (8) $5d 93 anc_data_5 [39:32] 0x00 r (8) $61 97 mfsdf (x) 0x07 r/w (8) $63 99 dac_clk_mode 0x00 r/w (8) $64 100 pllfrac_l 0x46 r/w (8) $65 101 pllfrac_h 0x5b r/w (8) $67 103 frame_cnt_l 0x00 r (8) $68 104 frame_cnt_m 0x00 r (8) $69 105 frame_cnt_h 0x00 r (8) $6a 106 average_bitrate 0x00 r (8) $71 113 softversion r (8) $72 114 run 0x00 r/w (8) $77 119 treble_frequency_low 0x00 r/w (8) $78 120 treble_frequency_high 0x00 r/w (8) $79 121 bass_frequency_low 0x00 r/w (8) $7a 122 bass_frequency_high 0x00 r/w (8) $7b 123 treble_enhance 0x00 r/w (8) $7c 124 bass_enhance 0x00 r/w (8) $7d 125 tone_atten 0x00 r/w (8) note: 1) the hex_cod is the hexadecimal adress that the microcontroller has to generate to access the information. 2) reserved: register used for production test only, or for future use. STA013 - STA013b - STA013t 12/38
4.1 - STA013 registers description the STA013 device includes 128 i 2 c registers. in this document, only the user-oriented registers are described. the undocumented registers are reserved. these registers must never be ac- cessed (in read or in write mode). the read- only registers must never be written. the following table describes the meaning of the abbreviations used in the i 2 c registers descrip- tion: symbol comment na not applicable und undefined nc no charge ro read only wo write only r/w read and write r/ws read, write in specific mode version address: 0x00 type: ro msb lsb b7 b6 b5 b4 b3 b2 b1 b0 v8 v7 v6 v5 v4 v3 v2 v1 the version register is read-only and it is used to identify the ic on the application board. ident address: 0x01 type: ro software reset: 0xac hardware reset: 0xac msb lsb b7 b6 b5 b4 b3 b2 b1 b0 10101100 ident is a read-only register and is used to iden- tify the ic on an application board. ident always has the value "0xac" pllctl address: 0x05 type: r/w software reset: 0x21 hardware reset: 0x21 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 xto_ buf xtod is oclk en sys2o clk ppld is xti2ds pclk xti2o clk upd_f rac upd_frac: when is set to 1, update frac in the switching circuit. it is set to 1 after autoboot. xti2oclk: when is set to 1, use the xti as input of the divider x instead of vco output. it is set to 0 on hw reset. xti2dspclk: when is to 1, set use the xti as in- put of the divider s instead of vco output. it is set to 0 on hw reset. plldis: when set to 1, the vco output is dis- abled. it is set to 0 on hw reset. sys2oclk: when is set to 1, the oclk fre- quency is equal to the system frequency. it is useful for testing. it is set to 0 on hw reset. oclken: when is set to 1, the oclk pad is en- able as output pad. it is set to 1 on hw reset. xtodis: when is set to 1, the xto pad is dis- able. it is set to 0 on hw reset. xto_buf: when this bit is set, the pin nr. 28 (out_clock/data_req) is enabled. it is set to 0 after autoboot. pllctl (m) address: 0x06 type: r/w software reset: 0x0c hardware reset: 0x0c pllctl (n) address: 0x07 type: r/w software reset: 0x00 hardware reset: 0x00 the m and n registers are used to configure the STA013 pll by dsp embedded software. m and n registers are r/w type but they are completely controlled, on STA013, by dsp soft- ware. req_pol address: 0x0c type: r/w software reset: 0x01 hardware reset: 0x00 STA013 - STA013b - STA013t 13/38
hardware reset: 0x01 the req_pol registers is used to program the polarity of the data_req line. msb lsb b7 b6 b5 b4 b3 b2 b1 b0 00000001 default polarity (the source sends data when the data_req line is high) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 00000101 inverted polarity (the source sends data when the data_req line is low) sckl_pol address: 0x0d type: r/w software reset: 0x04 hardware reset: 0x04 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 xxxxx00 0(1) 100(2) x = don?t care sckl_pol is used to select the working polarity of the input serial clock (sckr). (1) if sckl_pol is set to 0x00, the data (sdi) are sent with the falling edge of sckr and sampled on the rising edge. (2) if sckl_pol is set to 0x04, the data (sdi) are sent with the rising edge of sckr and sampled on the falling edge. error_code address: 0x0f type: ro software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 xxxx0 00 0(1) 0001(2) 0010(3) x = don?t care error_code register contains the last error occourred if any. the codes can be as follows: code description (1) 0x00 no error since the last sw or hw reset (2) 0x01 crc failure (3) 0x02 data not available soft_reset address: 0x10 type: wo software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 xxxxxxx0 1 x = don?t care; 0 = normal operation; 1 = reset when this register is written, a soft reset occours. the STA013 core command register and the in- terrupt register are cleared. the decoder goes in to idle mode. play address: 0x13 type: r/w software reset: 0x01 hardware reset: 0x01 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 xxxxxxx0 1 x = don?t care; 0 = normal operation; 1 = play the play command is handled according to the state of the decoder, as described in section 2.5. play only becomes active when the decoder is in decode mode. STA013 - STA013b - STA013t 14/38
data_req_enable address: 0x18 type: r/w software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description x x x x x 0 x x buffered output clock x x x x x 1 x x request signal mute address: 0x14 type: r/w software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 xxxxxxx0 1 x = don?t care; 0 = normal operation; 1 = mute the mute command is handled according to the state of the decoder, as described in section 2.5. mute sets the clock running. cmd_interrupt address: 0x16 type: r/w software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 xxxxxxx0 1 x = don?t care; 0 = normal operation; 1 = write into i 2 c/ancillary data the interrupt is used to give STA013 the command to write into the i2c/ancillary data buffer (registers: 0x59 ... 0x5d). every time the master has to extract the new buffer content (5 bytes) it writes into this register, setting it to a non-zero value. syncstatus address: 0x40 type: ro software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description xxxxxxss1ss0 0 0 research of sync word 0 1 wait for confirmation 1 0 synchronised 1 1 not used the data_req_enable register is used to configure pin n. 28 working as buffered output clock or data request signal, used for multimedia mode. the buffered output clock has the same fre- quency than the input clock (xti) STA013 - STA013b - STA013t 15/38
anccount_l address: 0x41 type: ro software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 ac7 ac6 ac5 ac4 ac3 ac2 ac1 ac0 anccount_h address: 0x42 type: ro software reset: 0x00 hardware reset: 0x00 anccount_h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 ac15 ac14 ac13 ac12 ac11 ac10 ac9 ac8 anccount registers are logically concatenated and indicate the number of ancillary data bits available at every correctly decoded mpeg frame. head_h[23:16] msb lsb b7 b6 b5 b4 b3 b2 b1 b0 x x x h20 h19 h18 h17 h16 x = don?t care head_m[15:8] msb lsb b7 b6 b5 b4 b3 b2 b1 b0 h15 h14 h13 h12 h1?1 h10 h9 h8 head_l[7:0] msb lsb b7 b6 b5 b4 b3 b2 b1 b0 h7 h6 h5 h4 h3 h2 h1 h0 address: 0x43, 0x44, 0x45 type: ro software reset: 0x00 hardware reset: 0x00 head[1:0] emphasis head[2] original/copy head[3] copyrighthead [5:4] mode extension head[7:6] mode head[8] private bit head[9] padding bit head[11:10] sampling frequency index head[15:12] bitrate index head[16] protection bit head[18:17] layer head[19] id head[20] id_ex the head registers can be viewed as logically concatenated to store the mpeg layer iii header content. the set of three registers is updated every time the synchronisation to the new mpeg frame is achieved STA013 - STA013b - STA013t 16/38
the meaning of the flags are shown in the follow- ing tables: mpeg ids idex id 0 0 mpeg 2.5 0 1 reserved 1 0 mpeg 2 1 1 mpeg 1 layer in layer iii these two flags must be set always to "01". protection_bit it equals "1" if no redundancy has been added and "0" if redundancy has been added. bitrate_index indicates the bitrate (kbit/sec) depending on the mpeg id. bitrate index id = 1 id = 0 ?0000? free free ?0001? 32 8 ?0010? 40 16 ?0011? 48 24 ?0100? 56 32 ?0101? 64 40 ?0110? 80 48 ?0111? 96 56 ?1000? 112 64 ?1001? 128 80 ?1010? 160 96 ?1011? 192 112 ?1100? 224 128 ?1101? 256 144 ?1110? 320 160 ?1111? forbidden forbidden sampling frequency indicates the sampling frequency of the encoded audio signal (khz) depending on the mpeg id sampling frequency mpeg1 mpeg2 mpeg2.5 ?00? 44.1 22.05 11.03 ?01? 48 24 12 ?10? 32 16 8 ?11? reserved reserved reserved padding bit if this bit equals ?1?, the frame contains an addi- tional slot to adjust the mean bitrate to the sam- pling frequency, otherwise this bit is set to ?0?. private bit bit for private use. this bit will not be used in the future by iso/iec. mode indicates the mode according to the following ta- ble. the joint stereo mode is intensity_stereo and/or ms_stereo. mode mode specified ?00? stereo ?01? joint stereo (intensity_stereo and/or ms_stereo) ?10? dual_channel ?11? single_channel (mono) mode extension these bits are used in joint stereo mode. they in- dicates which type of joint stereo coding method is applied. the frequency ranges, over which the intensity_stereo and ms_stereo modes are ap- plied, are implicit in the algorithm. copyright if this bit is equal to ?0?, there is no copyright on the bitstream, ?1? means copyright protected. original/copy this bit equals ?0? if the bitstream is a copy, ?1? if it is original. emphasis indicates the type of de-emphasis that shall be used. emphasis emphasis specified ?00? none ?01? 50/15 microseconds ?10? reserved ?11? ccitt j,17 STA013 - STA013b - STA013t 17/38
dla register is used to attenuate the level of audio output at the left channel using the butter- fly shown in fig. 12. when the register is set to 255 (0xff), the maximum attenuation is achieved. a decimal unit correspond to an attenuation step of 1 db. dla address: 0x46 type: r/w software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description dla7 dla6 dla5 dla4 dla3 dla2 dla1 dla0 output attenuation 00000000 no attenuation 00000001 -1db 00000010 -2db :::::::: : 01100000 - 96db dlb address: 0x47 type: r/w software reset: 0xff hardware reset: 0xff msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description dlb7 dlb6 dlb5 dlb4 dlb3 dlb2 dlb1 dlb0 output attenuation 00000000 no attenuation 00000001 -1db 00000010 -2db :::::::: : 01100000 - 96db dlb register is used to re-direct the left channel on the right, or to mix both the channels. default value is 0x00, corresponding at the maxi- mum attenuation in the re-direction channel. x dla + x output left channel dsp left channel dlb x dra + x output right channel dsp right channel drb d97au667 figure 12. volume control and output setup STA013 - STA013b - STA013t 18/38
dra address: 0x48 type: r/w software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description dra7 dra6 dra5 dra4 dra3 dra2 dra1 dra0 output attenuation 00000000 no attenuation 00000001 -1db 00000010 -2db :::::::: : 01100000 - 96db dra register is used to attenuate the level of audio output at the right channel using the but- terfly shown in fig. 11. when the register is set to 255 (0xff), the maximum attenuation is achieved. a decimal unit correspond to an attenuation step of 1 db. drb address: 0x49 type: r/w software reset: 0xff hardware reset: 0xff msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description drb7 drb6 drb5 drb4 drb3 drb2 drb1 drb0 output attenuation 00000000 no attenuation 00000001 -1db 00000010 -2db :::::::: : 01100000 - 96db drb register is used to re-direct the right chan- nel on the left, or to mix both the channels. default value is 0x00, corresponding at the maxi- mum attenuation in the re-direction channel. mfsdf_441 address: 0x50 type: r/w software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 x x x m4 m3 m2 m1 m0 this register contains the value for the pll x driver for the 44.1khz reference frequency. the vco output frequency, when decoding 44.1khz bitstream, is divided by (mfsdf_441 +1) pllfrac_441_l address: 0x51 type: r/w software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 STA013 - STA013b - STA013t 19/38
pllfrac_441_h address: 0x52 type: r/w software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 pf15 pf14 pf13 pf12 pf11 pf10 pf9 pf8 the registers are considered logically concate- nated and contain the fractional values for the pll, for 44.1khz reference frequency. (see also pllfrac_l and pllfrac_h regis- ters) pcmdivider address: 0x54 type: rw software reset: 0x03 hardware reset: 0x03 76543210 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pcmdivider is used to set the frequency ratio between the oclk (oversampling clock for dacs), and the sckt (serial audio transmitter clock). the relation is the following: sckt_freq = oclk_freq 2 ( 1 + pcm_div ) the oversampling factor (o_fac) is related to oclk and sckt by the following expression: 1) oclk_freq = o_fac * lrckt_ freq (dac relation) 2) oclk_ freq = 2 * (1+pcm_div) * 32* lrckt_freq (when 16 bit pcm mode is used) 3) oclk_ freq = 2 * (1+pcm_div) * 64* lrckt_freq (when 32 bit pcm mode is used) 4) pcm_div = (o_fac/64) - 1 in 16 bit mode 5) pcm_div = (o_fac/128) - 1 in 32 bit mode example for setting: msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 0000011116 bit mode 512 x fs 0000010116 bit mode 384 x fs 0000001116 bit mode 256 x fs 0000001132 bit mode 512 x fs 0000001032 bit mode 384 x fs 0000000132 bit mode 256 x fs for 16 bit pcm mode o_fac = 512 ; pcm_div = 7 o_fac = 256 ; pcm_div = 3 o_fac = 384 ; pcm_div = 5 for 32 bit pcm mode o_fac = 512 ; pcm_div = 3 o_fac = 256 ; pcm_div = 1 o_fac = 384 ; pcm_div = 2 STA013 - STA013b - STA013t 20/38
pcmconf address: 0x55 type: r/w software reset: 0x21 hardware reset: 0x21 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description x ord dif inv for scl prec (1) prec (1) x 1 pcm order the ls bit is transmitted first x 0 pcm order the ms bit is transmitted first x 0 the word is right padded x 1 the word is left padded x 1 lrckt polarity compliant to i2s format x 0 lrckt polarity inverted x 0 i2s format x 1 different formats x 1 data are sent on the rising edge of sckt x 0 data are sent on the falling edge of sckt x 0 0 16 bit mode (16 slots transmitted) x 0 1 18 bit mode (18 slots transmitted) x 1 0 20 bit mode (20 slots transmitted) x 1 1 24 bit mode (24 slots transmitted) pcmconf is used to set the pcm output inter- face configuration: ord: pcm order. if this bit is set to?1?, the ls bit is transmitted first, otherwise ms bit is transmiited first. dif: pcm_diff. it is used to select the position of the valid data into the transmitted word. this setting is significant only in 18/20/24 bit/word mode.if it is set to ?0? the word is right-padded, otherwise it is left-padded. inv (fig.13): it is used to select the lrckt clock polarity. if it is set to ?1? the polarity is compliant to i2s format (low -> left , high -> right), otherwise the lrckt is inverted. the default value is ?0?. (if i2s have to be selected, must be set to ?1? in the STA013 configuration phase). for: format is used to select the pcm output interface format. after hw and sw reset the value is set to 0 corre- sponding to i 2 s format. scl (fig.14): used to select the transmitter serial clock polarity. if set to ?1? the data are sent on the rising edge of sckt and sampled on the falling. if set to ?0? , the data are sent on the falling edge and sampled on the rising. this last option is the most commonly used by the commercial dacs. the default configuration for this flag is ?0?. prec [1:0]: pcm precision it is used to select the pcm samples precision, as follows: ?00?: 16 bit mode (16 slots transmitted) ?01?: 18 bit mode (32 slots transmitted) ?10?: 20 bit mode (32 slots transmitted) ?11?: 24 bit mode (32 slots transmitted) the pcm samples precision in STA013 can be 16 or 18-20-24 bits. when STA013 operates in 16 (18-20-24) bits mode, the number of bits transmitted during a lrclt period is 32 (64). lrckt lrckt inv_lrclk=0 left left ri g ht ri g ht left left inv_lrclk=1 figure 13. lrckt polarity selection inv_sclk=0 sckt sdo figure 14. sckt polarity selection inv_sclk=1 sckt sdo STA013 - STA013b - STA013t 21/38
pcmcross address: 0x56 type: r/w software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 description x x x x x x 0 0 left channel is mapped on the left output. right channel is mapped on the right output x x x x x x 0 1 left channel is duplicated on both output channels. x x x x x x 1 0 right channel is duplicated on both output channels x x x x x x 1 1 right and left channels are toggled the default configuration for this register is ?0x00?. ancillary data buffer address: 0x59 - 0x5d type: ro software reset: 0x00 hardware reset: 0x00 STA013 can extract max 56 bytes/mpeg frame. to know the number of a.d. bits available every mpeg frame, the anccount_l and anc- count_h registers (0x41 and 0x42) have to be read. the buffer dimension is 5 bytes, written by STA013 core in sequential order. the timing in- formation to read the buffer can be obtained by reading the frame_cnt registers (0x67 - 0x69). to fill up the buffer with a new 5-bytes slot, the STA013 waits until a cmd_interrupt register is written by the master. mfsdf (x) address: 0x61 type: r/w software reset: 0x07 hardware reset: 0x07 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 x x x m4 m3 m2 m1 m0 the register contains the values for pll x divider (see fig. 7). the value is changed by the internal STA013 core, to set the clocks frequencies, according to the incoming bitstream. this value can be even set by the user to select the pcm interface con- figuration. the vco output frequency is divided by (x+1). this register is a reference for 32khz and 48 khz input bitstream. dac_clk_mode address: 0x63 type: rw software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 xxxxxxxmode this register is used to select the operating mode for oclk clock signal. if it is set to ?1?, the oclk frequency is fixed, and it is mantained to the value fixed by the user even if the sampling frequency of the incoming bit- stream changes. it the mode flag is set to ?0?, the oclk frequency changes, and can be set to (512, 384, 256) * fs. the default configuration for this mode is 256 * fs. when this mode is selected, the default oclk frequency is 12.288 mhz. STA013 - STA013b - STA013t 22/38
pllfrac_l ([7:0]) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 pllfrac_h ([15:8]) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 pf15 pf14 pf13 pf12 pf11 pf10 pf9 pf8 address: 0x64 - 0x65 type: r/w software reset: 0x46 | 0x5b hardware reset: 0xna | 0x5b the registers are considered logically concate- nated and contain the fractional values for the pll, used to select the internal configuration. after reset, the values are na, and the opera- tional setting are done when the mpeg synchro- nisation is achieved. the following formula describes the relationships among all the STA013 fractional pll parameters: oclk_freq = ? ? ? 1 x + 1 ? ? ? ? ? ? ? mclk_freq n + 1 ? ? ? ? ? ? ? m + 1 + frac 65536 ? ? ? where: frac=256 x frac_h + frac_l (decimal) these registers are a reference for 48 / 24 / 12 / 32 / 16 / 8khz audio. frame_cnt_l msb lsb b7 b6 b5 b4 b3 b2 b1 b0 fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 frame_cnt_m msb lsb b7 b6 b5 b4 b3 b2 b1 b0 fc15 fc14 fc13 fc12 fc11 fc10 fc9 fc8 frame_cnt_h msb lsb b7 b6 b5 b4 b3 b2 b1 b0 fc23 fc22 fc21 fc20 fc19 fc18 fc17 fc016 address: 0x67, 0x68, 0x69 type: ro software reset: 0x00 hardware reset: 0x00 the three registers are considered logically con- catenated and compose the global frame counter as described in the table. it is updated at every decoded mpeg frame. the registers are reset on both hardware and software reset. average_bitrate address: 0x6a type: ro software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 ab7 ab6 ab5 ab4 ab3 ab2 ab1 ab0 average_bitrate is a read-only register and it contains the average bitrate of the incoming bit- stream. the value is rounded with an accuracy of 1 kbit/sec. softversion address: 0x71 type: ro msb lsb b7 b6 b5 b4 b3 b2 b1 b0 sv7 sv6 sv5 sv4 sv3 sv2 sv1 sv0 after the STA013 boot, this register contains the version code of the embedded software. STA013 - STA013b - STA013t 23/38
run address: 0x72 type: rw software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 xxxxxxxrun setting this register to 1, STA013 leaves the idle state, starting the decoding process. the microcontroller is allowed to set the run flag, once all the control registers have been in- itialized. treble_frequency_low address: 0x77 type: rw software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 tf7 tf6 tf5 tf4 tf3 tf2 tf1 tf0 treble_frequency_high address: 0x78 type: rw software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 tf15 tf14 tf13 tf12 tf11 tf10 tf9 tf8 the registers treble_frequency-high and treble_frequency-low, logically concate- nated as a 16 bit wide register, are used to select the frequency, in hz, where the selected fre- quency is +12db respect to the stop band. by setting these registers, the following rule must be kept: treble_freq < fs/2 bass_frequency_low address: 0x79 software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 bf7 bf6 bf5 bf4 bf3 bf2 bf1 bf0 bass_frequency_high address: 0x7a software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 bf15 bf14 bf13 bf12 bf11 bf10 bf9 bf8 the registers bass_frequency_high and bass_frequency_low, logically concate- nated as a 16 bit wide register, are used to select the frequency, in hz, where the selected fre- quency is -12db respect to the pass-band. by setting the bass_frequency registers, the following rules must be kept: bass_freq <= treble_freq bass_freq > 0 (suggested range: 20 hz < bass_freq < 750 hz) example: bass = 200hz treble = 3khz tfs 1514131211109876543210 0000101110111000 bfs 1514131211109876543210 0000000011001000 STA013 - STA013b - STA013t 24/38
treble_enhance address: 0x7b software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 te7 te6 te5 te4 te3 te2 te1 te0 signed number (2 complement) this register is used to select the enhancement or attenuation STA013 has to perform on treble frequency range at the digital signal. a decrement (increment) of a decimal unit corre- sponds to a step of attenuation (enhancement) of 1.5db. the allowed attenuation/enhancement range is [-18db, +18db]. msb lsb enhance/attenuation b7 b6 b5 b4 b3 b2 b1 b0 1.5db step 00001100 +18 00001011 +16.5 00001010 +15 00001001 +13.5 . . . 00000001 +1 00000000 0 11111111 -1 . . . 11110111 -13.5 11110110 -15 11110100 -16.5 11110100 -18 STA013 - STA013b - STA013t 25/38
bass_enhance address: 0x7c software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 be7 be6 be5 be4 be3 be2 be1 be0 signed number (2 complement) this register is used to select the enhancement or attenuation STA013 has to perform on bass frequency range at the digital signal. a decrement (increment) of a decimal unit corre- sponds to a step of attenuation (enhancement) of 1.5db. the allowed attenuation/enhancement range is [-18db, +18db]. msb lsb enhance/attenuation b7 b6 b5 b4 b3 b2 b1 b0 1.5db step 00001100 +18 00001011 +16.5 00001010 +15 00001001 +13.5 . . . 00000001 +1 00000000 0 11111111 -1 . . . 11110111 -13.5 11110110 -15 11110100 -16.5 11110100 -18 STA013 - STA013b - STA013t 26/38
tone_atten address: 0x7d type: rw software reset: 0x00 hardware reset: 0x00 msb lsb b7 b6 b5 b4 b3 b2 b1 b0 ta7 ta6 ta5 ta4 ta3 ta2 ta1 ta0 in the digital output audio, the full signal is achieved with 0 db of attenuation. for this rea- son, before applying bass & treble control, the user has to set the tone_atten register to the maximum value of enhancement is going to per- form. for example, in case of a 0 db signal (max. level) only attenuation would be possible. if enhance- ment is desired, the signal has to be attenuated accordingly before in order to reserve a margin in db. an increment of a decimal unit corresponds to a tone attenuation step of 1.5db. msb lsb attenuation b7 b6 b5 b4 b3 b2 b1 b0 -1.5db step 00000000 0db 00000001 -1.5db 00001010 -3db 00000011 -4.5db . . . 00001010 -15db 00001011 -16.5db 00001100 -18db demultiplexing & error check huffman decoding d98au903 inverse quantisation & descaling side information decoding inverse filterbank imdct stereophonic audio signal (2*768kbit/s) encoded audio bitstream (8kbit/s ... 128kbit/s) ancillary data 5.1. mpeg 2.5 layer iii algorithm. 5.2 - mpeg ancillary data description: as specifyed in the iso standard, the mpeg layer iii frames have a variable bit lenght, and are constant in time depending on the audio sam- pling frequencies. the time duration of the layer iii frames is shown in tab 2. 5. general information table2: mpeg layer iii frames time duration sampling frequency (khz) 48 44.1 32 24 22.5 16 12 11.025 8 mpeg frame lenght (ms) 24 29 36 24 29 36 48 48 72 STA013 - STA013b - STA013t 27/38
the ancillary data extraction on STA013 can be described as follow: STA013 has a specific ancillary data buffer, mapped into the i2c registers: 0x59 anc_data_1 0x5a anc_data_2 0x5b anc_data_3 0x5c anc_data_4 0x5d anc_data_5 since the content of ancillary data into an mpeg frame STA013 can extract is max. 56 bytes, a specific register, to require the new 5 byte slot to sta003 is needed. this register is: 0x16 cmd_interrupt the interrupt register, is sensitive to any non-zero value written by the microcontroller. when this register is updated the ancillary data buffer is filled up with new values and the registers 0x41 anccount_l 0x42 anccount_h are updated (decremented) accordingly. 5.3. i/o cell description 1) cmos tristate output pad buffer , 4ma, with slew rate control / pin numbers 9, 10, 11, 20, 28 en a d98au904 z output pin max load z 100pf 2) cmos bidir pad buffer , 4ma, with slew rate control / pin numbers 3, 12 en a d98au905 zi io output pin capacitance output pin max load io 5pf io 100pf 3) cmos inpud pad buffer / pin numbers 4, 5, 6, 8, 21, 25 a d98au906 z input pin capacitance a 3.5pf 4) cmos inpud pad buffer with active pull-up / pin numbers 7, 24, 26 a d98au907 z input pin capacitance a 3.5pf STA013 - STA013b - STA013t 28/38
5.4. timing diagrams 5.4.1. audio dac interface a) oclk in output. the audio pll is used to clock the dac oclk (output) sdo sckt lrclk t sdo t sckt t lrclk d98au969 pad-timing versus load load (pf) pad_timing 25 2.90ns 50 3.82ns 75 4.68ns 100 5.52ns cload_xxx is the load in pf on the xxx output. pad_timing (cload_xxx) is the propagation delay added to the xxx pad due to the load. tsdo = 3.5 + pad_timing (cload_sdo) - pad_timing (cload_ oclk) tsckt = 4 + pad_timing (cload_sckt) - pad_timing (cload_ oclk) tlrckt = 3.5 + pad_timing (cload_lrcckt) - pad_timing (cload_ oclk) oclk (input) sdo sckt lrclk t sdo t sckt t lrclk d98au970 t hi t lo t oclk b) oclk in input. thi min = 3ns tlo min = 3ns toclk min = 25ns tsdo = 5.5 + pad_timing (cload_sdo) ns tsckt = 6 + pad_timing (cload_sckt) ns tlrckt = 5.5 + pad_timing (cload_lrckt) ns STA013 - STA013b - STA013t 29/38
sdi sckr ignored valid ignored t _biten t _biten t sdi_hold t sdi_setup d98au971a t sckr_min_high bit_en sclk_pol=0 t sckr_min_low t sckr_min_period 5.4.2. bitstream input interface (sdi, sckr, bit_en) scl_pol = 0 tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns src_int d98au972 t _src_hi t _src_low 5.4.3. src_int this is an asynchronous input used in "broadcast? mode. src_int is active low t_src_low min duration is 50ns (1dsp clock period) t_src_high min duration is 50ns (1dsp clock period) xti (input) xto clk_out t xto t clk_out d98au973 t hi t lo 5.4.4. xti,xto and clk_out timings txto = 1.40 + pad_timing (cload_xto) ns tclk_out = 4 + pad_timing (cload_clk_out) ns note: in "multimedia" mode, the clk_out pad is data_req. in that case, no timing is given between the xti input and this pad. sdi sckr ignored ignored valid ignored t _biten t _biten t sdi_hold t sdi_setup d99au1038 t sckr_min_high bit_en sclk_pol=4 t sckr_min_low t sckr_min_period 5.4.2. bitstream input interface (sdi, sckr, bit_en) scl_pol = 1 STA013 - STA013b - STA013t 30/38
reset d98au974 t reset_low_min 5.4.5. reset the reset min duration (t_reset_low_min) is 100ns hw reset set pcm output interface configuration set set pcm-divider pcm-conf. pll frac_441_h, pll frac_441_l, pll frac_h, pll frac_l } { set mfs df_441, mfsdf } { pll configuration for: set pll ctrl 48, 44.1, 32 29, 22.05, 16 12, 11.025, 8 } khz ? { set sclk_pol input serial clock polarity configuration set data_req_enable data request pin enable set req_pol data request polarity configuration run set ? multimedia mode see {tab 5 to tab12} the overall setting steps are included in the STA013 configuration file and can be downloaded in one step. stm provides a specific configuration file for each supported input clock frequency d98au975 5.5. configuration flow STA013 - STA013b - STA013t 31/38
table 5: pll configuration sequence for 10mhz input clock 256 oversapling clock register address name value 6 reserved 18 11 reserved 3 97 mfsdf (x) 15 80 mfsdf-441 16 101 pllfrac-h 169 82 pllfrac-441-h 49 100 pllfrac-l 42 81 pllfrac-441-l 60 5 pllctrl 161 table 6: pll configuration sequence for 10mhz input clock 384 oversapling rathio register address name value 6 reserved 17 11 reserved 3 97 mfsdf (x) 9 80 mfsdf-441 10 101 pllfrac-h 110 82 pllfrac-441-h 160 100 pllfrac-l 152 81 pllfrac-441-l 186 5 pllctrl 161 table 7: pll configuration sequence for 14.31818mhz input clock 256 oversapling rathio register address name value 6 reserved 12 11 reserved 3 97 mfsdf (x) 15 80 mfsdf-441 16 101 pllfrac-h 187 82 pllfrac-441-h 103 100 pllfrac-l 58 81 pllfrac-441-l 119 5 pllctrl 161 table 8: pll configuration sequence for 14.31818mhz input clock 384 oversapling rathio register address name value 6 reserved 11 11 reserved 3 97 mfsdf (x) 6 80 mfsdf-441 7 101 pllfrac-h 3 82 pllfrac-441-h 157 100 pllfrac-l 211 81 pllfrac-441-l 157 5 pllctrl 161 STA013 - STA013b - STA013t 32/38
table 9: pll configuration sequence for 14.31818mhz input clock 512 oversapling rathio register address name value 6 reserved 11 11 reserved 3 97 mfsdf (x) 6 80 mfsdf-441 7 101 pllfrac-h 3 82 pllfrac-441-h 157 100 pllfrac-l 211 81 pllfrac-441-l 157 5 pllctrl 161 table 10: pll configuration sequence for 14.7456mhz input clock 256 oversapling rathio register address name value 6 reserved 12 11 reserved 3 97 mfsdf (x) 15 80 mfsdf-441 16 101 pllfrac-h 85 82 pllfrac-441-h 4 100 pllfrac-l 85 81 pllfrac-441-l 0 5 pllctrl 161 table 11: pll configuration sequence for 14.7456mhz input clock 384 oversapling rathio register address name value 6 reserved 10 11 reserved 3 97 mfsdf (x) 8 80 mfsdf-441 9 101 pllfrac-h 64 82 pllfrac-441-h 124 100 pllfrac-l 0 81 pllfrac-441-l 0 5 pllctrl 161 table 12: pll configuration sequence for 14.7456mhz input clock 512 oversapling rathio register address name value 6 reserved 9 11 reserved 2 97 mfsdf (x) 5 80 mfsdf-441 6 101 pllfrac-h 0 82 pllfrac-441-h 184 100 pllfrac-l 0 81 pllfrac-441-l 0 5 pllctrl 161 STA013 - STA013b - STA013t 33/38
5.6. STA013 configuration file format the STA013 configuration file is an ascii format. an example of the file format is the following: 58 1 42 4 128 15 ............ it is a sequence of rows and each one can be interpreted as an i 2 c command. the first part of the row is the i 2 c address (register) and the second one is the i 2 c data (value). to download the STA013 configuration file into the device, a sequence of write operation to STA013 i 2 c interface must be performed. the following program describes the i 2 c routine to be implemented for the configuration driver: STA013 configuration code (pse udo code) download cfg - file { fopen (cfg_file); fp:=1; /*set file pointer to first row */ do { i 2 c_start_cond; /* generate i 2 c start condition for STA013 device address */ i 2 c_write_dev_addr; /* write STA013 device address */ i 2 c_write_subaddress (fp); /* write subaddress */ i 2 c_write_data (fp); /* write data */ i 2 c_stop_cond; /* generate i 2 c stop condition */ fp++; /* update pointer to new file row */ } while (!edf) /* repeat until end of file */ } /* end routine */ 42 4 i 2 c register value i 2 c sub-address d98au976 note:1 STA013 is a device based on an integrated dsp core. some of the i2c registers default values are loaded after an internal dsp b oot operation. the bootstrap time is 60 micro second. only after this time lenght, the data in the register can be considered stable. note 2 : refer also to the application note 1090 STA013 - STA013b - STA013t 34/38
so28 dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) outline and mechanical data STA013 - STA013b - STA013t 35/38
outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.30 0.37 0.45 0.012 0.015 0.018 c 0.09 0.20 0.004 0.008 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 8.00 0.315 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 8.00 0.315 e 0.80 0.031 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.039 k 0?(min.), 3.5?(typ.), 7?(max.) tqfp44 (10 x 10 x 1.4mm) a a2 a1 b seating plane c 11 12 22 23 33 34 44 e1 e d1 d e 1 k b tqfp4410 l 0.10mm .004 0076922 d STA013 - STA013b - STA013t 36/38
outline and mechanical data d1 d a 0.15 a1 a2 e f f a 1 2 3 4 5 6 7 8 b c d e f g h e1 b (64 places) e ball 1 identification lfbga64m dim. mm inch min. typ. max. min. typ. max. a 1.700 0.067 a1 0.350 0.400 0.450 0.014 0.016 0.018 a2 1.100 0.043 b 0.500 0.20 d 8.000 0.315 d1 5.600 0.220 e 0.800 0.031 e 8.000 0.315 e1 5.600 0.220 f 1.200 0.047 lfbga64 body: 8 x 8 x 1.7mm STA013 - STA013b - STA013t 37/38
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this p ublication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia ? belgium - brazil - canada - china ? czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com STA013 - STA013b - STA013t 38/38

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